A PLL is an electronic circuit which is widely used to generate highly stable signals for electronic and communication devices, such as wireless telephones and the like. More specifically, a PLL is used to control the frequency of a signal generated by a voltage controlled oscillator (xe2x80x9cVCOxe2x80x9d) or the like. VCOs are used in almost every communications device. For example, wireless telephones communicate with one another and with wireless networks using signals generated by VCOs embedded within such telephones. The signals generated by VCOs are then used to transmit voice and data messages.
Today""s modem communication devices require that signals generated by a VCO be stable and accurate. That is, for a telephone to work properly, for a telephone to communicate with another wireless telephone or a wireless network a VCO""s signal must be accurate (i.e., maintained within a narrow range).
Enter the PLL. A simplified, typical PLL circuit 100 is shown in FIG. 1. As shown, a VCO 1 outputs a signal (referred to as xe2x80x9cVCOout-freqxe2x80x9d) along pathway 8. This signal may be any frequency, but for the following example, it will be assumed to be in megahertz (xe2x80x9cMHzxe2x80x9d). This is a fair assumption considering the typical frequencies used by wireless devices. It should be understood that the present invention envisions frequencies in the MHz and gigahertz (xe2x80x9cGHzxe2x80x9d) range as well, however. That said, strictly speaking, the methods and devices envisioned by the present invention can utilize any frequency, not just MHz or GHz.
To insure that the signal output by the VCO 1 remains accurate, its output is also fed back to a MAIN counter 2 along pathway 9a. This counter 2 is designed to accept VCOout-freq and to divide this frequency down by an amount dictated by a MAIN counter setting to generate a xe2x80x9cPMxe2x80x9d signal 7b. The PM signal is one of two signals input into a phase detector 11. The second signal is input from a reference counter (xe2x80x9cREF counterxe2x80x9d) 3. The REF counter 3 also supplies a signal (xe2x80x9cPRxe2x80x9d) 7a along pathway 10a. The signal supplied by the REF counter 3 originates with a signal generator 5 which is adapted to output a signal whose frequency is maintained within a specific, narrow range. It can be said that the signal generator 5 acts as a reference source. That is, the output of the VCO 1 can be compared against the signal output from the signal generator 5 to make sure the frequency of the signal output by the VCO 1 stays within an acceptable range.
Backtracking somewhat, the REF counter 3 and MAIN counter 2 are adapted to divide down the frequencies of their respective inputs 9a, 9b such that:
PRfreq=REF INfreq/REFsettingxe2x80x83xe2x80x83(1)
and
PMfreq=VCOout-freq/MAINsettingxe2x80x83xe2x80x83(2)
where PRfreq is the frequency of the PR signal 7a output from the REF counter 3; REF INfreq is the frequency of the signal 9b input from the signal generator 5; REFsetting is an amount that controls the xe2x80x9cdivide downxe2x80x9d function of the REF counter 3; PMfreq is the frequency of the PM signal 7b output from the MAIN counter 2; MAINsetting is an amount that controls the xe2x80x9cdivide downxe2x80x9d function of the MAIN counter 2; and VCOout-freq is the frequency of the signal input into the MAIN counter 2 from the VCO 1 along pathway 9a. 
In a typical PLL, the REF counter 3 and MAIN counter 2 settings are intentionally set so that the PRfreq and PMfreq are exactly equal. This implies:
REF INfreq/REFcounter setting=VCOout-freq/MAINsetting.xe2x80x83xe2x80x83(3)
As shown in FIG. 1, the phase detector 11 is adapted to receive both the PR 7a and PM 7b signals. Thereafter, the phase detector 11 is further adapted to output a signal 7c based on the frequency and phase of the PR and PM signals 7a, 7b. For example, if the PR and PM signals have the same frequency and phase, the phase detector will not output a signal. As is known in the art, loop filter 6 typically comprises a capacitance whose stored charge maintains a constant voltage input into VCO 1 (i.e., xe2x80x9cthe loop is considered lockedxe2x80x9d). However, if the PR and PM signals 7a, 7b are not in agreement, the phase detector 11 is adapted to output an error signal to the charge pump 4. Upon receipt of this error signal, the charge pump 4 is adapted to supply a necessary current to the loop filter 6 which in turn adjusts the voltage which is input into the VCO 1. By changing the voltage input into the VCO 1, the frequency of VCOout-freq is changed. This change in frequency is designed to xe2x80x9cdrivexe2x80x9d or control the operation of the VCO 1 so that VCOout-freq remains stable. Said another way, the PLL is considered stable when the PR and PM signals agree in frequency and phase. When this occurs, VCOout-freq will be maintained at a stable, set value.
From equation (3), VCOout-freq can be defined as:
VCOout-freq=REF INfreq*MAINsetting/REFcounter setting.xe2x80x83xe2x80x83(4)
As may be apparent from the discussion above, to insure that the correct adjustment is made to the VCO 1, it was assumed that the MAIN and REF counters 2,3 were operating accurately. If either one or both of the counters are not operating accurately, then it will be difficult to correctly adjust the VCO 1.
Many things may cause a MAIN or REF counter to output an inaccurate signal. Sometimes the counter becomes inoperative over time. More frequently, however, a counter is operating correctly but receives a signal (e.g., from a VCO or another source) which causes it to output an inaccurate signal. For example, design limitations may dictate that the MAIN counter 2 shown in FIG. 1 will output a PM signal only after receiving a signal from the VCO 1 which is greater than a certain threshold. If the VCO output (which is input into the MAIN counter 2) falls below this threshold, no PM signal will be output. In actuality, there is an upper and lower limit to this threshold such that only those signals falling within the range of signals between both limits will cause the MAIN counter 2 to output a PM signal. The lower limit is known as the xe2x80x9csensitivityxe2x80x9d of a counter while the upper limit is known as the xe2x80x9csaturationxe2x80x9d of a counter.
On occasion, however, a signal falls just below or just above the limits of a counter. Sometimes these signals are so close to either limit that they trigger the counter to output a signal. These circumstances typically occur intermittently and are, for the most part, unpredictable. Nonetheless, to the extent possible, it is important to know when such circumstances might occur because once a counter has output an erroneous PM or PR signal it will adversely affect the ultimate frequency output by a VCO.
Realizing this, most manufacturers test REF and MAIN counters to determine whether they will produce miscounts when signals below, within or above the sensitivity and saturation limits are applied to the counters.
Up until now, however, the techniques used to test for such miscounts have been inadequate. Sometimes the techniques lack the ability to detect such intermittent miscounts. Other times, these techniques require additional circuitry. In each case, the techniques are xe2x80x9cclosed loopxe2x80x9d. That is, the techniques require a MAIN counter to be connected to a VCO forming a closed loop.
Accordingly, it is desirable to provide for methods and devices for testing the operation of counters used in PLLs which are capable of detecting intermittent miscounts.
It is also desirable to provide for methods and devices for testing the operation of counters used in PLLs which do not require a closed loop.
Other desires, features and advantages of the present invention will become apparent to those skilled in the art from the following description taken in conjunction with the accompanying drawings.
In accordance with the present invention there are provided methods and devices for testing the operation of MAIN and REF counters used in a PLL.
To test the operation of these counters, including, but not limited to their sensitivity and saturation limits, first and second signal generators feed first and second signals into MAIN and REF counters, respectively. The frequency of the PM and PR signals are offset slightly to generate a difference signal which, when integrated, comprises a predetermined, small beat frequency waveform, such as a sawtooth waveform. This predetermined waveform comprises a predictable slope.
The first or second signals are then adjusted or altered to test the limits of the MAIN or REF counter. When an adjustment causes one of the counters to miscount, an altered, integrated signal will be output from a charge pump.
This altered waveform is compared to the predetermined waveform to test the limits of both counters.
The present invention and its advantages can be best understood with reference to the drawings, detailed description of the preferred embodiments and claims that follow.